In the TFT-LCD, a basic principle for displaying picture in each frame is as follows: a source driver outputs data signals required by pixels in each row sequentially row-by-row, while a gate driver gates the pixels in each row by inputting a square wave having a certain width to gates of the pixels in each row sequentially row-by-row.
A traditional method is to bind a gate driver IC and a source driver IC on a glass panel by a Chip on Glass (COG) process. However, during an actual manufacturing process, when a resolution of the TFT-LCD is high, the number of output lines for gate driving is large and a length of the gate driver IC may be increased, which may not only increase difficulty in the COG process, but also reduce an excellent rate of the products.
To this end, those skilled in the art proposed a technique of Gate Driver on Array (thereafter will be called as GOA briefly) which manufactures the gate driver IC on the glass panel by an array process. This technique may reduce cost of product, increase reliability of the panel, and also may decrease the difficulty in an IC binding for the TFT-LCD having small size.
Shift registers are used to form a gate driving circuit for generating waves required at gates in the GOA technique. FIG. 1 is a diagram illustrating a circuit principle of an existing shift register. Referring FIG. 1, the shift register comprises four transistors and two capacitors, each of the transistors comprises a gate, a source and a drain. Wherein a drain of the first transistor T1, a source of the second transistor T2, a gate of the third transistor T3, a first terminal of the first capacitor C1 and a first terminal of the second capacitor C2 converge to form a node P. A gate and a source of the first transistor T1 are connected with each other and serve as a signal input terminal STV of the shift register; a drain of the first transistor T1 is connected to the source of the second transistor T2; a gate of the second transistor T2 is connected to a gate of the fourth transistor T4 and receives a reset signal Reset externally, a drain of the second transistor T2 receives a low level signal Voff from an external circuit; a source of the third transistor T3 receives a second clock signal CLK2 from the external circuit, the gate of the third transistor T3 is connected to a node P, and a drain of the third transistor T3 is connected to a source of the fourth transistor T4 and a second terminal of the second capacitor C2 and serves as an output terminal Row of the shift register; the gate of the fourth transistor T4 is connected to the gate of the second transistor T2, the drain of the fourth transistor T4 is connected to the drain of the second transistor T2 and receives the low level signal Voff from the external circuit; the second terminal of the first capacitor C1 is connected to a first clock signal CLK1, the first terminal thereof is connected to the node P; the first terminal of the second capacitor C2 is connected to the node P, and the second terminal thereof is connected to the source of the third transistor T3 and the source of the fourth transistor T4.
However, a clock frequency used in the above shift register is high, such that the gate driving circuit for generating waves required at gates not only has high power consumption and a poor capability of anti-interference, but also has a small output power and more big burrs. Further, floating may occur at the output terminal of the shift register sometimes, which may lead to an unstable output wave.